1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory, which comprises memory cells each including a ferroelectric capacitor and a transistor.
2. Description of the Related Art
A ferroelectric memory (FeRAM) is such a semiconductor memory device that utilizes the hysteresis characteristic of a ferroelectric capacitor to store data nonvolatilely in accordance with two different polarization magnitudes of the ferroelectric material.
A memory cell in a ferroelectric memory of the conventional art is generally configured to use the same architecture as a DRAM. That is, a paraelectric capacitor is replaced with a ferroelectric capacitor and the ferroelectric capacitor is serially connected to a selection transistor. Such memory cells are arranged plural in grid to configure a memory cell array. In data reading and so forth, the word line (selection line) related to a memory cell aimed at reading and so forth is raised to turn on the selection transistor, which connects the memory cell to a bit line. Then, while a plate line voltage is applied to a plate line, a variation in voltage caused on the bit line in accordance with the residual polarization of the ferroelectric capacitor is sensed/amplified at a sense amp for data reading.
In the above structure, however, an increase in bit line capacitance prevents application of a sufficient voltage across terminals of the ferroelectric capacitor and results in insufficient reading of residual polarization information, which disadvantageously leads to a smaller amount of read signals (problem 1). In addition, variations in temperature, variations over time, and so forth may change the hysteresis characteristic of the ferroelectric capacitor. In such the case, either in a memory cell holding “0” data or in a memory cell holding “1” data, a variation in read voltage occurs and disadvantageously makes it difficult to set the reference voltage in the sense amp (problem 2).
In contrast, JP 2002-133857A proposes a ferroelectric memory, which uses a scheme that keeps the bit line voltage at 0 on reading. In this scheme, all pieces of residual polarization information about the ferroelectric capacitor can be read out. Accordingly, the above problem 1 can be solved but the above problem 2 can not be solved yet.
On the other hand, there is another scheme as proposed by Yeonbae Chung et al., “A 3.3-V, 4 Mb nonvolatile ferroelectric RAM with selectively driven double pulsed plate read/write-back scheme”, IEEE journal of solid-state circuits, Vol. 35, No. 5, PP/697-704, 2000. This scheme raises a plate line voltage once to read out the charge and then lowers the plate line voltage again to the ground potential for sensing in this state. In this scheme, the bit line associated with the memory cell holding “0” data is surely kept at 0 V. Accordingly, the problem 2 can be solved but the problem 1 still remains.